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New class of hardware-Level fault-tolerant Quantum-Computing Devices
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New class of hardware-Level fault-tolerant Quantum-Computing Devices 

[Submitted on 6 Jul 2022 (v1), last revised 7 Jul 2022 (this version, v2)]

Authors:Morteza Aghaee, Arun Akkala, Zulfi Alam, Rizwan Ali, Alejandro Alcaraz Ramirez, Mariusz Andrzejczuk, Andrey E Antipov, Pavel Aseev, Mikhail Astafev, Bela Bauer, Jonathan Becker, Srini Boddapati, Frenk Boekhout, Jouri Bommer, Esben Bork Hansen, Tom Bosma, Leo Bourdet, Samuel Boutin, Philippe Caroff, Lucas Casparis, Maja Cassidy, Anna Wulf Christensen, Noah Clay, William S Cole, Fabiano Corsetti, Ajuan Cui, Paschalis Dalampiras, Anand Dokania, Gijs de Lange, Michiel de Moor, Juan Carlos Estrada Saldaña, Saeed Fallahi, Zahra Heidarnia Fathabad, John Gamble, Geoff Gardner, Deshan Govender, Flavio Griggio, Ruben Grigoryan, Sergei Gronin, Jan Gukelberger, Sebastian Heedt, Jesús Herranz Zamorano, Samantha Ho, Ulrik Laurens Holgaard, William Hvidtfelt Padkær Nielsen, Henrik Ingerslev, Peter Jeppesen Krogstrup, Linda Johansson, Jeffrey Jones, Ray Kallaher, Farhad Karimi, Torsten Karzig, Cameron King, Maren Elisabeth Kloster, Christina Knapp, Dariusz Kocon, Jonne Koski, Pasi Kostamo, Mahesh Kumar, Tom Laeven, Thorvald Larsen, Kongyi Li, Tyler Lindemann, Julie Love, Roman Lutchyn, Michael Manfra, Elvedin Memisevic, Chetan Nayak, Bas Nijholt, Morten Hannibal Madsen, Signe Markussen, Esteban Martinez, Robert McNeil, Andrew Mullally, Jens Nielsen, Anne Nurmohamed, Eoin O’Farrell, Keita Otani, Sebastian Pauka, Karl Petersson, Luca Petit, Dima Pikulin, Frank Preiss, Marina Quintero Perez, Katrine Rasmussen, Mohana Rajpalke, Davydas Razmadze, Outi Reentila, David Reilly, Richard Rouse, Ivan Sadovskyy, Lauri Sainiemi, Sydney Schreppler, Vadim Sidorkin, Amrita Singh, Shilpi Singh, Sarat Sinha, Patrick Sohr, Tomaš Stankevič, Lieuwe Stek


et al. (27 additional authors not shown)

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Abstract: We present measurements and simulations of semiconductor-superconductor
heterostructure devices that are consistent with the observation of topological
superconductivity and Majorana zero modes. The devices are fabricated from
high-mobility two-dimensional electron gases in which quasi-one-dimensional
wires are defined by electrostatic gates. These devices enable measurements of
local and non-local transport properties and have been optimized via extensive
simulations for robustness against non-uniformity and disorder. Our main result
is that several devices, fabricated according to the design’s engineering
specifications, have passed the topological gap protocol defined in Pikulin
{it et al.} [arXiv:2103.12217]. This protocol is a stringent test composed of
a sequence of three-terminal local and non-local transport measurements
performed while varying the magnetic field, semiconductor electron density, and
junction transparencies. Passing the protocol indicates a high probability of
detection of a topological phase hosting Majorana zero modes. Our experimental
results are consistent with a quantum phase transition into a topological
superconducting phase that extends over several hundred millitesla in magnetic
field and several millivolts in gate voltage, corresponding to approximately
one hundred micro-electron-volts in Zeeman energy and chemical potential in the
semiconducting wire. These regions feature a closing and re-opening of the bulk
gap, with simultaneous zero-bias conductance peaks at {it both} ends of the
devices that withstand changes in the junction transparencies. The measured
maximum topological gaps in our devices are 20-$30,mu$eV. This demonstration
is a prerequisite for experiments involving fusion and braiding of Majorana
zero modes.

Submission history

From: Chetan Nayak [view email]

[v1]
Wed, 6 Jul 2022 06:40:12 UTC (9,338 KB)
[v2]
Thu, 7 Jul 2022 21:54:11 UTC (9,326 KB)

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